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(R)
ISL6262A
Data Sheet December 23, 2008 FN6343.1
Two-Phase Core Controller (Santa Rosa, IMVP-6+)
The ISL6262A is a two-phase buck converter regulator implementing Intel(R) IMVP-6+ protocol with embedded gate drivers. The two-phase buck converter uses two interleaved channels to effectively double the output voltage ripple frequency, and thereby reduce output voltage ripple amplitude with fewer components; lower component cost; reduced power dissipation; and smaller real estate area. The heart of the ISL6262A is the patented R3 TechnologyTM, Intersil's Robust Ripple Regulator modulator. Compared with the traditional multiphase buck regulator, the R3 TechnologyTM has the fastest transient response. This is due to the R3 modulator commanding variable switching frequency during a load transient. Intel(R) Mobile Voltage Positioning (IMVP) is a smart voltage regulation technology, which effectively reduces power dissipation in Intel(R) Pentium processors. To boost battery life, the ISL6262A supports DPRSLPVR (deeper sleep), DPRSTP# and PSI# functions, and maximizes the efficiency via automatically enabling different phase operation modes. At heavy load operation of the active mode, the regulator commands the two phase continuous conduction mode (CCM) operation. While the PSI# is asserted with medium load in active mode, the ISL6262A smoothly disables one phase and operates in one-phase CCM. When the CPU enters deeper sleep mode, the ISL6262A enables diode emulation to maximize the efficiency at light load. For better system power management of the portable computer, the ISL6262A also provides a CPU power monitor output. The analog output at the power monitor pin can be fed into an A/D converter to report instantaneous or average CPU power. A 7-bit digital-to-analog converter (DAC) allows dynamic adjustment of the core output voltage from 0.300V to 1.500V. A 0.5% system accuracy of the core output voltage over-temperature is achieved by the ISL6262A. A unity-gain differential amplifier is provided for remote CPU die sensing. This allows the voltage on the CPU die to be accurately measured and regulated per Intel(R) IMVP-6+ specifications. Current sensing can be realized using either lossless inductor DCR sensing, or precision resistor sensing. A single NTC thermistor network thermally compensates the gain and the time constant of the DCR variations.
Features
* Precision Two/One-phase CORE Voltage Regulator - 0.5% System Accuracy Over-Temperature - Enhanced Load Line Accuracy * Internal Gate Driver with 2A Driving Capability * Dynamic Phase Adding/Dropping * Microprocessor Voltage Identification Input - 7-Bit VID Input - 0.300V to 1.500V in 12.5mV Steps - Support VID Change On-the-Fly * Multiple Current Sensing Schemes Supported - Lossless Inductor DCR Current Sensing - Precision Resistive Current Sensing * CPU Power Monitor * Thermal Monitor * User Programmable Switching Frequency * Differential Remote CPU Die Voltage Sensing * Static and Dynamic Current Sharing * Overvoltage, Undervoltage, and Overcurrent Protection * Pb-Free (RoHS Compliant)
Ordering Information
PART NUMBER (Note) ISL6262ACRZ PART MARKING TEMP. RANGE (C) PACKAGE (Pb-Free) PKG. DWG. #
ISL6262 ACRZ -10 to +100 48 Ld 7x7 QFN L48.7x7
ISL6262ACRZ-T* ISL6262 ACRZ -10 to +100 48 Ld 7x7 QFN L48.7x7 ISL6262AIRZ ISL6262 AIRZ -40 to +100 48 Ld 7x7 QFN L48.7x7 -40 to +100 48 Ld 7x7 QFN L48.7x7
ISL6262AIRZ-T* ISL6262 AIRZ
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved. R3 TechnologyTM is a trademark of Intersil Americas Inc. Intel(R) is a registered trademark of Intel Corporation. All other trademarks mentioned are the property of their respective owners.
ISL6262A Pinout
ISL6262A (48 LD 7x7 QFN) TOP VIEW
DPRSLPVR DPRSTP# CLK_EN# VR_ON
VID6
VID5
VID4
VID3
VID2
VID1 38
48 PGOOD PSI# PMON RBIAS VR_TT# NTC SOFT OCSET VW 1 2 3 4 5 6 7 8 9
47
46
45
44
43
42
41
40
39
37 36 BOOT1 35 UGATE1 34 PHASE1 33 PGND1 32 LGATE1
VID0 31 PVCC 30 LGATE2 29 PGND2 28 PHASE2 27 UGATE2 26 BOOT2 25 NC 24 ISEN1
3V3
GND PAD (BOTTOM)
COMP 10 FB 11 FB2 12 13 VDIFF 14 VSEN 15 RTN 16 DROOP 17 DFB 18 VO 19 VSUM 20 VIN 21 GND 22 VDD 23 ISEN2
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FN6343.1 December 23, 2008
ISL6262A
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V Boot to Phase Voltage (BOOT to PHASE . . . . . . -0.3V to +7V (DC) -0.3V to +9V (<10ns) Phase Voltage (PHASE) . . . . . . . . . -7V (<20nS Pulse Width, 10J) UGATE Voltage (UGATE) . . . . . . . . . . PHASE -0.3V (DC) to BOOT . . . . . . . . . . . . . PHASE-5V (<20nS Pulse Width, 10J) to BOOT LGATE Voltage (LGATE) . . . . . . . . . . . . -0.3V (DC) to (VDD +0.3V) . . . . . . . . . . . . . . -2.5V (<20nS Pulse Width, 5J) to (VDD +0.3V) All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V) Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . -0.3 to +7V
Thermal Information
Thermal Resistance (Typical) JAC/W JCC/W QFN Package (Notes 1, 2). . . . . . . . . . 29 4.5 Maximum Storage Temperature Range . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5% Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 25V Ambient Temperature Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10C to +100C Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +100C Junction Temperature Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10C to +125C Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +125C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VDD = 5V, TA = -40C to +100C, unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER INPUT POWER SUPPLY +5V Supply Current
IVDD
VR_ON = 3.3V VR_ON = 0V
3.6
4.1 1 1 1
mA A A A V V
+3.3V Supply Current Battery Supply Current at VIN pin POR (Power-On Reset) Threshold
I3V3 IVIN PORr PORf
No load on CLK_EN# VR_ON = 0V, VIN = 25V VDD Rising VDD Falling 4.0 4.35 4.15
4.5
SYSTEM AND REFERENCES System Accuracy %Error (VCC_CORE) ISL6262ACRZ No load, closed loop, active mode, TA = 0C to +100C, VID = 0.75 to 1.5V VID = 0.5 to 0.7375V VID = 0.3 to 0.4875V System Accuracy %Error (VCC_CORE) ISL6262AIRZ No load, closed loop, active mode, TA = -40C to +100C, VID = 0.75 to 1.5V VID = 0.5 to 0.7375V VID = 0.3 to 0.4875V Droop Amplifier Offset RBIAS Voltage Boot Voltage Maximum Output Voltage RRBIAS VBOOT VCC_CORE (max) VCC_CORE (min) VID Off State VID = [0000000] VID = [1100000] VID = [1111111] RRBIAS = 147k -0.5 -8 -15 -0.8 -10 18 0.3 1.45 1.188 1.47 1.2 1.5 0.3 0 0.5 8 15 0.8 10 18 0.3 1.49 1.212 V V V V V mV % mV mV %
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FN6343.1 December 23, 2008
ISL6262A
Electrical Specifications
VDD = 5V, TA = -40C to +100C, unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER CHANNEL FREQUENCY Nominal Channel Frequency Adjustment Range AMPLIFIERS Droop Amplifier Offset Error Amp DC Gain Error Amp Gain-Bandwidth Product Error Amp Slew Rate FB Input Current ISEN Imbalance Voltage Input Bias Current SOFT-START CURRENT Soft-Start Current Soft Geyserville Current Soft Deeper Sleep Entry Current Soft Deeper Sleep Exit Current Soft Deeper Sleep Exit Current GATE DRIVER DRIVING CAPABILITY UGATE Source Resistance UGATE Source Current UGATE Sink Resistance UGATE Sink Current LGATE Source Resistance LGATE Source Current LGATE Sink Resistance LGATE Sink Current UGATE to PHASE Resistance
fSW
RFSET = 6.9k, 2 channel operation, VCOMP = 2V
285 100
300
315 500
kHz kHz
-0.3 AV0 GBW SR IIN(FB) CL = 20pF CL = 20pF 90 18 5 10
0.3
mV dB MHz V/s
150
nA
2 20
mV nA
ISS IGV IC4 IC4EA IC4EB |SOFT - REF|>100mV DPRSLPVR = 3.3V DPRSLPVR = 3.3V DPRSLPVR = 0V
-47 180 -47 37 180
-42 205 -42 42 205
-37 230 -37 47 230
A A A A A
RSRC(UGATE) ISRC(UGATE) RSNK(UGATE) ISNK(UGATE) RSRC(LGATE) ISRC(LGATE) RSNK(LGATE) ISNK(LGATE) Rp(UGATE)
500mA Source Current VUGATE_PHASE = 2.5V 500mA Sink Current VUGATE_PHASE = 2.5V 500mA Source Current VLGATE = 2.5V 500mA Sink Current VLGATE = 2.5V
1 2 1 2 1 2 0.5 4 1
1.5
A
1.5
A
1.5
A
0.9
A k
GATE DRIVER SWITCHING TIMING (refer to "ISL6262A Gate Driver Timing Diagram" on page 6) UGATE Rise Time LGATE Rise Time UGATE Fall Time LGATE Fall Time UGATE Turn-on Propagation Delay LGATE Turn-on Propagation Delay BOOTSTRAP DIODE Forward Voltage Leakage POWER GOOD and PROTECTION MONITOR PGOOD Low Voltage PGOOD Leakage Current VOL IOH IPGOOD = 4mA PGOOD = 3.3V -1 0.26 0.4 1 V A VDDP = 5V, Forward Bias Current = 2mA VR = 16V 0.43 0.58 0.72 1 V A tRU tRL tFU tFL tPDHU tPDHU PVCC = 5V, 3nF Load PVCC = 5V, 3nF Load PVCC = 5V, 3nF Load PVCC = 5V, 3nF Load PVCC = 5V, Outputs Unloaded PVCC = 5V, Outputs Unloaded 8.0 8.0 8.0 4.0 30 15 ns ns ns ns ns ns
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FN6343.1 December 23, 2008
ISL6262A
Electrical Specifications
VDD = 5V, TA = -40C to +100C, unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL tpgd OVH OVHS TEST CONDITIONS CLK_EN# Low to PGOOD High VO rising above setpoint >1ms VO rising above setpoint >0.5s I (RBIAS) = 10A DROOP rising above OCSET >120s Difference between ISEN1 and ISEN2 >1ms UVf VO falling below setpoint for >1ms -360 MIN 6.3 160 1.675 9.8 -3.5 9 -300 -240 TYP 7.6 200 1.7 10 MAX 8.9 240 1.725 10.2 3.5 UNITS ms mV V A mV mV mV
PARAMETER PGOOD Delay Overvoltage Threshold Severe Overvoltage Threshold OCSET Reference Current OC Threshold Offset Current Imbalance Threshold Undervoltage Threshold (VDIFF-SOFT) LOGIC INPUTS VR_ON, DPRSLPVR Input Low VR_ON, DPRSLPVR Input High Leakage Current of VR_ON
VIL(3.3V) VIH(3.3V) IIL(3.3V) IIH(3.3V) Logic input is low Logic input is high at 3.3V -1 2.3 -1 0 0 0 0.45
1
V V A
1
A A
Leakage Current of DPRSLPVR
IIL_DPRSLP(3.3V) DPRSLPVR input is low IIH_DPRSLP(3.3V) DPRSLPVR input is high at 3.3V
1 0.3
A V V
DAC(VID0-VID6), PSI# and DPRSTP# Input Low DAC(VID0-VID6), PSI# and DPRSTP# Input High Leakage Current of DAC(VID0VID6), PSI# and DPRSTP# THERMAL MONITOR NTC Source Current Over-Temperature Threshold VR_TT# Low Output Resistance POWER MONITOR PMON Output Voltage Range
VIL(1V) VIH(1V) IIL(1V) IIH(1V) Logic input is low Logic input is high at 1V 0.7 -1 0 0.45
A 1 A
NTC = 1.3V V(NTC) falling RTT I = 20mA
53 1.18
60 1.2 6.5
67 1.22 9
A V
Vpmon
VSEN = 1.2V, Droop - VO = 80mV VSEN = 1V, Droop - VO = 20mV
1.638 0.308 2.8
1.680 0.350 3.0
1.722 0.392
V V V mA mA
PMON Maximum Voltage PMON Sourcing Current PMON Sinking Current Maximum Current Sinking Capability PMON Impedance
Vpmonmax Isc_pmon Isk_pmon VSEN = 1V, Droop - VO = 50mV VSEN = 1V, Droop - VO = 50mV (see Figure 31) When PMON is within its sourcing/sinking current range (Established by characterization)
2 2 PMON/ 250 PMON/ 180 7 PMON/ 130
A
CLK_EN# OUTPUT LEVELS CLK_EN# High Output Voltage CLK_EN# Low Output Voltage VOH VOL 3V3 = 3.3V, I = -4mA ICLK_EN# = 4mA 2.9 3.1 0.26 0.4 V V
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FN6343.1 December 23, 2008
ISL6262A ISL6262A Gate Driver Timing Diagram
PWM
tPDHU tRU UGATE 1V
tFU
LGATE
1V tRL tPDHL
tFL
Functional Pin Description
DPRSLPVR DPRSTP# CLK_EN# VR_ON
VID6
VID5
VID4
VID3
VID2
VID1 38
48 PGOOD PSI# PMON RBIAS VR_TT# NTC SOFT OCSET VW 1 2 3 4 5 6 7 8 9
47
46
45
44
43
42
41
40
39
37 36 BOOT1 35 UGATE1 34 PHASE1 33 PGND1 32 LGATE1
VID0 31 PVCC 30 LGATE2 29 PGND2 28 PHASE2 27 UGATE2 26 BOOT2 25 NC 24 ISEN1
3V3
GND PAD (BOTTOM)
COMP 10 FB 11 FB2 12 13 VDIFF 14 VSEN 15 RTN 16 DROOP 17 DFB 18 VO 19 VSUM 20 VIN 21 GND 22 VDD 23 ISEN2
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FN6343.1 December 23, 2008
ISL6262A
PGOOD - Power good open-drain output. Connect externally with 680 to VCCP or 1.9k to 3.3V. PSI# - Current indicator input. When asserted low, indicates a reduced load-current condition and initiates single-phase operation. PMON - Analog output. PMON is proportional to the product of Vsen and droop voltage. RBIAS - 147k resistor to GND sets internal current reference. VR_TT# - Thermal overload output indicator with open-drain output. Over-temperature pull-down resistance is 10. NTC - Thermistor input to VRTT# circuit and a 60A current source is connected internally to this pin. SOFT - A capacitor from this pin to GND sets the maximum slew rate of the output voltage. SOFT is the non-inverting input of the error amplifier. OCSET - Overcurrent set input. A resistor from this pin to VO sets DROOP voltage limit for OC trip. A 10A current source is connected internally to this pin. VW - A resistor from this pin to COMP programs the switching frequency (for example, 6.82k 300kHz). COMP - This pin is the output of the error amplifier. FB - This pin is the inverting input of error amplifier. FB2 - There is a switch between FB2 pin and the FB pin. The switch is closed in single-phase operation and is opened in two phase operation. The components connecting to FB2 are to adjust the compensation in single phase operation to achieve optimum performance. VDIFF - This pin is the output of the differential amplifier. VSEN - Remote core voltage sense input. RTN - Remote core voltage sense return. DROOP - Output of the droop amplifier. The voltage level on this pin is the sum of VO and the droop voltage. DFB - Inverting input to droop amplifier. VO - An input to the IC that reports the local output voltage. VSUM - This pin is connected to the summation junction of channel current sensing. VIN - Battery supply voltage. It is used for input voltage feed-forward to improve input line transient performance. GND - Signal ground. Connect to local controller ground. VDD - 5V control power supply. ISEN2 - Individual current sharing sensing for Channel 2. If ISEN2 is pulled to 5V, phase 2's gate signals are disabled. ISL6262A is then configured in always-1-phase mode. ISEN1 - Individual current sharing sensing for Channel 1. N/C - Not connected. Grounding this pin to signal ground in the practical layout. BOOT2 - This pin is the upper gate driver supply voltage for phase 2. An internal boot strap diode is connected to the PVCC pin. UGATE2 - Upper MOSFET gate signal for phase 2. PHASE2 - The phase node of phase 2. Connect this pin to the source of the Channel 2 upper MOSFET. PGND2 - The return path of the lower gate driver for phase 2. LGATE2 - Lower-side MOSFET gate signal for phase 2. PVCC - 5V power supply for gate drivers. LGATE1 - Lower-side MOSFET gate signal for phase 1. PGND1 - The return path of the lower gate driver for phase 1. PHASE1 - The phase node of phase 1. Connect this pin to the source of the Channel 1 upper MOSFET. UGATE1 - Upper MOSFET gate signal for phase 1. BOOT1 - This pin is the upper-gate-driver supply voltage for phase 1. An internal boot strap diode is connected to the PVCC pin. VID0, VID1, VID2, VID3, VID4, VID5, VID6 - VID input with VID0 is the least significant bit (LSB) and VID6 is the most significant bit (MSB). VR_ON - Digital enable input. A logic high signal on this pin enables the regulator. DPRSLPVR - Deeper sleep enable signal. A logic high signal on this pin indicates the micro-processor is in deeper-sleep mode and also indicates a slow C4 entry or exit rate with 41A discharging or charging the SOFT capacitor. DPRSTP# - Deeper sleep slow wake up signal. A logic low signal on this pin indicates the micro-processor is in deeper-sleep mode. CLK_EN# - Digital output for system clock. Goes active 13 clks after Vcore is within 10% of Boot voltage. 3V3 - 3.3V supply voltage for CLK_EN#.
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FN6343.1 December 23, 2008
ISL6262A Functional Block Diagram
PHASE1 PHASE2 UGATE1 UGATE2 LGATE1 VR_TT# LGATE2 PVCC PGND1 PGND2 BOOT1 BOOT2 PVCC DRIVER LOGIC FLT ISEN2 ISEN1 CURRENT BALANCE VSOFT I_BALF VIN MODULATOR OC 3V3 CH1 PGOOD PGOOD MONITOR AND LOGIC CH1 CH2 Vw PHASE CONTROL LOGIC PHASE SEQUENCER VO VIN SINGLE PHASE VSOFT OC VO SOFT SINGLE PHASE + MULTIPLIER E/A + SINGLE PHASE FB2 FB SOFT PMON VDIFF CH2 Vw OC VW VSOFT VIN MODULATOR GND ULTRASONIC TIMER DRIVER LOGIC FLT
6A
54A PVCC PVCC VDD VIN VIN 1.2V PVCC 1.24V +
NTC
PVCC
CLK_EN#
COMP
FLT
PGOOD FAULT AND PGOOD LOGIC
+
MODE CHANGE REQUEST
1 0.66 + -
+ 1 RTN + VO
DACOUT
RBIAS
DAC
OCSET
+
MODE CONTROL
DROOP 10A -
VSEN VO
VR_ON
DPRSLPVR
DPRSTP#
VSUM
VID0
VID1
VID2
VID3
VID4
VID5
VID6
PSI#
DFB
FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL6262A
8
DROOP
FN6343.1 December 23, 2008
ISL6262A Typical Performance Curves 300kHz Operation, 2xIRF7821 as Upper Devices and 2xIRF7832 as Bottom Devices
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 5 10 15 20 25 IOUT (A) 30 35 40 45 50 1.04 1.02 VIN = 8.0V 1.14 VIN = 12.6V VIN = 19.0V VOUT (V) 1.12 1.10 VIN = 19.0V 1.08 1.06 VIN = 12.6V 1.16 VIN = 8.0V
0
10
20 IOUT (A)
30
40
50
FIGURE 2. ACTIVE MODE EFFICIENCY, 2 PHASE, CCM, PSI# = HIGH, VID = 1.15V
FIGURE 3. ACTIVE MODE LOAD LINE, 2 PHASE, CCM, PSI# = HIGH, VID = 1.15V
100 90 80 EFFICIENCY (%) 70 VOUT (V) 60 50 40 30 20 10 0 0 2 4 6 8 10 IOUT (A) 12 14 16 18 20 VIN = 19.0V VIN = 8.0V
1.16 1.15 VIN = 12.6V 1.14 1.13 VIN = 8.0V 1.12 1.11 1.10 VIN = 12.6V VIN = 19.0V
0
2
4
6
8
10 IOUT (A)
12
14
16
18
20
FIGURE 4. ACTIVE MODE EFFICIENCY, 1 PHASE, CCM, PSI# = LOW, VID = 1.15V
FIGURE 5. ACTIVE MODE LOAD LINE, 1 PHASE, CCM, PSI# = LOW, VID = 1.15V
100
0.765 0.760 VIN = 8.0V 0.755 VIN = 19.0V VIN = 12.6V VOUT (V)
90 EFFICIENCY (%)
80
0.750 0.745
VIN = 8.0V VIN = 19.0V
70
60
0.740 0.735 VIN = 12.6V 0 2 4 IOUT (A) 6 8 10
50 0.1
1.0 IOUT (A)
10
FIGURE 6. DEEPER SLEEP MODE EFFICIENCY
FIGURE 7. DEEPER SLEEP MODE LOAD LINE
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FN6343.1 December 23, 2008
ISL6262A Typical Performance Curves
0.36H Filter Inductor and 4 x 330F Output SP Caps and 24 x 22F Ceramic Caps
VOUT
VSOFT VR_ON
VOUT VR_ON
VSOFT
CSOFT = 15nF
CSOFT = 15nF
FIGURE 8. SOFT-START WAVEFORM SHOWING SLEW RATE OF 2.5mV/s AT VID = 1V, ILOAD = 10A
FIGURE 9. SOFT-START WAVEFORM SHOWING SLEW RATE OF 2.5mV/s AT VID = 1.4375V, ILOAD = 10A
VOUT @ 1.4375V VOUT @ 1.2V
PGD_IN IMVP-6+_PWRGD CLK_EN#
FIGURE 10. SOFT-START WAVEFORM SHOWING CLK_EN# AND IMVP-6+ PGOOD
FIGURE 11. 2 PHASE CURRENT BALANCE, FULL LOAD (50A)
IIN
LINE TRANSIENT VOUT
VOUT
VIN
IL1, IL2
IIN
FIGURE 12. 8V-20V INPUT LINE TRANSIENT RESPONSE, CIN = 240F
FIGURE 13. INRUSH CURRENT AT START-UP, VIN = 8V, VID = 1.4375V, ILOAD = 10A
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FN6343.1 December 23, 2008
ISL6262A Typical Performance Curves
0.36H Filter Inductor and 4 x 330F Output SP Caps and 24 x 22F Ceramic Caps (Continued)
VID3 VOUT VOUT
DYNAMIC VID ACTIVE MODE LOAD TRANSIENT PHASE1, PHASE2
FIGURE 14. LOAD STEP-UP RESPONSE AT THE CPU SOCKET MPGA479, 35A LOAD STEP @ 200A/s, 2 PHASE CCM
FIGURE 15. VID3 CHANGE OF 010X000 FROM 1V TO 1.1V WITH DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1
VID3 VOUT VOUT
DYNAMIC VID ACTIVE MODE LOAD TRANSIENT PHASE1, PHASE2
FIGURE 16. LOAD DUMP RESPONSE AT THE CPU SOCKET MPGA479, 35A LOAD STEP @ 200A/s, 2 PHASE CCM
FIGURE 17. VID3 CHANGE OF 010X000 FROM 1.1V TO 1V WITH DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1
PSI# VCORE
DROP PHASE IN ACTIVE MODE
PSI#
ADD PHASE IN ACTIVE MODE
VCORE
PHASE1
PHASE1
PHASE2
PHASE2
FIGURE 18. 2-CCM TO 1-CCM UPON PSI# ASSERTION WITH VID LSB CHANGE, AT DPRSLPVR = 0, DPRSTP# = 1, ILOAD = 10A
FIGURE 19. 1-CCM TO 2-CCM UPON PSI# DEASSERTION WITH VID LSB CHANGE AT DPRSLPVR = 0, DPRSTP# = 1
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FN6343.1 December 23, 2008
ISL6262A Typical Performance Curves
DPRSLPVR
0.36H Filter Inductor and 4 x 330F Output SP Caps and 24 x 22F Ceramic Caps (Continued)
DPRSLPVR C4 EXIT/PHASE ADD
VOUT C4 ENTRY WITH PSI# ASSERTION VOUT
PHASE1 PHASE2
PHASE1
PHASE2
FIGURE 20. C4 ENTRY WITH VID CHANGE 0011X00 FROM 1.2V TO 1.15V, ILOAD = 2A, TRANSITION OF 2-CCM TO 1-DCM, PSI# TOGGLE FROM 1 TO 0 WITH DPRSLPVR FROM 0 TO 1
FIGURE 21. VID3 CHANGE OF 010X000 FROM 1V TO 1.1V WITH DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1
DPRSTP# DPRSTP# DPRSLPVR DPRSLPVR VID6 VID6
DPRSLPVR
VOUT
C4 ENTRY WITH PSI# = 0
VCORE Vcore
PHASE1
PHASE2
FIGURE 22. SLOW C4 EXIT WITH DELAY OF DPRSLPVR, FROM VID1000000 (0.7V) TO 0110000 (0.9V)
FIGURE 23. C4 ENTRY WITH VID CHANGE OF 011X011 FROM 0.8625V TO 0.7625V, ILOAD = 3A, 1-CCM TO 1-DCM
VOUT PGOOD PGOOD
PHASE1
VOUT
IL1, IL2
FIGURE 24. OVERCURRENT PROTECTION
FIGURE 25. 1.7V OVERVOLTAGE PROTECTION SHOWS OUTPUT VOLTAGE PULLED LOW TO 0.9V AND PWM THREE-STATE
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ISL6262A Typical Performance Curves
0.36H Filter Inductor and 4 x 330F Output SP Caps and 24 x 22F Ceramic Caps (Continued)
VCORE Vcore VCORE Vcore
PMON PMON
PMON PMON
PMON AFTER 40kHz FILTER PMON after 40 kHz filter PMON AFTER 40kHZ FILTER PMON after 40 kHz filter
FIGURE 26. VID TRANSITION FROM 1V TO 1.15V ILOAD = 21A, EXTERNAL FILTER 40k AND 100pF AT PMON
FIGURE 27. VID = 1.15V, LOAD TRANSIENT OF 0A TO 36A WITH INTEL(R) VTT TOOL, 1kHz REPETITION RATE, 50% DUTY CYCLE, TR = 56
VCORE Vcore VCORE Vcore
PMON PMON
PMON PMON
PMON AFTER 40 kHz filter PMON after40kHZ FILTER
PMON after 40 kHz filter
FIGURE 28. VID = 1.15V, LOAD RELEASE FROM 36A TO 0A WITH INTEL(R) VTT TOOL, 1kHz REPETITION RATE, 50% DUTY CYCLE, TR = 56 FIGURE 29. VID = 1.15V, LOAD APPLICATION FROM 0A TO 36A WITH INTEL(R) VTT TOOL, 1kHz REPETITION RATE, 50% DUTY CYCLE, TR = 56
PMON AFTER 40kHZ FILTER
1.8 1.6 1.4 1.2 PMON (V) 1.0 0.8 0.6 0.4 0.2 0.0 0.0 PMON (V) 19V, 1.15V, 30A 19V, 1.15V, 40A 7
0.8 0.7 0.6 0.5 0.4 0.3 0.2 19V, 1.15V, 10A 19V, 1.15V, 5A 1.0 2.0 3.0 4.0 5.0 6.0 7.0 CURRENT SOURCING (mA) 0.1 0.00 0.0 0.5 VID = 1.15V, IOUT = 5A VID = 1.15V, IOUT = 2.5A 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VID = 1.15V, IOUT = 10A 180 VID = 1.15V, IOUT = 15A
19V, 1.15V, 20A
CURRENT SINKING (mA)
FIGURE 30. POWER MONITOR CURRENT SOURCING CAPABILITY
FIGURE 31. POWER MONITOR CURRENT SINKING CAPABILITY
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ISL6262A Simplified Application Circuit for DCR Current Sensing
V +5
V +3.3
VIN
R12
3V3 RBIAS NTC
VDD PVCC VIN VIN
ISL6262A
VR_TT#
R13 VR_TT# C8 SOFT VIDs PHASE1 UGATE1 BOOT1 C6
C7
LO
VID<0:6>
R10 DPRSTP# DPRSLPVR PSI# DPRSTP# LGATE1 DPRSLPVR PGND1 PSI# PMON CLK_ENABLE# VR_ON IMVP-6+_PWRGD REMOTE SENSE R2 VDIFF R3 C3 R7 C1 C2 RFSET VW OCSET C9 GND DFB DROOP VO R5 R6 R4 C4 RN NTC NETWORK CCS CLK_EN# VR_ON PGOOD VSEN UGATE2 RTN BOOT2 C5 PHASE2 R11 FB2 FB R1 COMP ISEN2 VSUM VSUM LGATE2 PGND2 R9 RL ISEN2 CL VO' LO VIN C8 ISEN1 CO ISEN1 R8 VSUM VO' VO RL CL
VSUM
VO'
FIGURE 32. ISL6262A BASED TWO-PHASE BUCK CONVERTER WITH INDUCTOR DCR CURRENT SENSING
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ISL6262A Simplified Application Circuit for Resistive Current Sensing
V +5
V +3.3
VIN
R11
3V3 RBIAS NTC
VDD PVCC VIN VIN
ISL6262A
VR_TT#
R12 VR_TT# C9 SOFT VIDs PHASE1 UGATE1 BOOT1 C6
C7
L
RS
VID<0:6>
R10 DPRSTP# DPRSLPVR PSI# DPRSTP# LGATE1 DPRSLPVR PGND1 PSI# PMON CLK_ENABLE# VR_ON IMVP-6+_PWRGD REMOTE SENSE R2 VDIFF R3 C3 R7 C1 C2 RFSET VW OCSET C9 GND DFB DROOP VO R5 R6 R4 C4 CHF CLK_EN# VR_ON PGOOD VSEN UGATE2 RTN BOOT2 C5 PHASE2 R11 FB2 FB R1 COMP ISEN2 VSUM VSUM LGATE2 PGND2 R9 RL ISEN2 CL VO' L RS VIN C8 ISEN1 CO ISEN1 R8 VSUM VO' VO RL CL
VSUM
VO'
FIGURE 33. ISL6262A BASED TWO-PHASE BUCK CONVERTER WITH RESISTIVE CURRENT SENSING
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ISL6262A Theory of Operation
The ISL6262A is a two-phase regulator implementing Intel IMVP-6+ protocol and includes embedded gate drivers for reduced system cost and board area. The regulator provides optimum steady-state and transient performance for microprocessor core applications up to 50A. System efficiency is enhanced by idling one phase at low-current and implementing automatic DCM-mode operation. The heart of the ISL6262A is R3 TechnologyTM, Intersil's Robust Ripple Regulator modulator. The R3 modulator combines the best features of fixed frequency PWM and hysteretic PWM while eliminating many of their shortcomings. The ISL6262A modulator internally synthesizes an analog of the inductor ripple current and uses hysteretic comparators on those signals to establish PWM pulse widths. Operating on these large-amplitude, noise-free synthesized signals allows the ISL6262A to achieve lower output ripple and lower phase jitter than either conventional hysteretic or fixed frequency PWM controllers. Unlike conventional hysteretic converters, the ISL6262A has an error amplifier that allows the controller to maintain a 0.5% voltage regulation accuracy throughout the VID range from 0.75V to 1.5V. The hysteresis window voltage is relative to the error amplifier output such that load current transients results in increased switching frequency, which gives the R3 regulator a faster response than conventional fixed frequency PWM controllers. Transient load current is inherently shared between active phases due to the use of a common hysteretic window voltage. Individual average phase voltages are monitored and controlled to equally share the static current among the active phases.
VDD 10mV/s VR_ON 100s SOFT AND VO 2mV/s VBOOT 90% VID COMMANDED VOLTAGE
13 SWITCHING CYCLES CLK_EN#
IMVP-6+ PGOOD
-7ms
FIGURE 34. SOFT-START WAVEFORMS USING A 20nF SOFT CAPACITOR
Static Operation
After the start sequence, the output voltage will be regulated to the value set by the VID inputs shown in Table 1. The entire VID table is presented in the IntelIMVP-6+ specification. The ISL6262A will control the no-load output voltage to an accuracy of 0.5% over the range of 0.75V to 1.5V.
TABLE 1. TRUNCATED VID TABLE FOR INTEL(R) IMVP-6+ SPECIFICATION VID6 0 0 0 0 0 VID5 0 0 0 0 0 1 1 1 1 VID4 0 0 0 1 1 1 1 0 1 VID3 0 0 0 0 1 0 1 0 1 VID2 0 0 1 0 1 1 0 0 1 VID1 0 0 0 0 0 0 1 0 1 VID0 VOUT (V) 0 1 1 1 0 1 1 0 1 1.5000 1.4875 1.4375 1.2875 1.15 0.8375 0.7625 0.3000 0.0000
Start-Up Timing
With the controller's +5V VDD voltage above the POR threshold, the start-up sequence begins when VR_ON exceeds the 3.3V logic HIGH threshold. Approximately 100s later, SOFT and VOUT begin ramping to the boot voltage of 1.2V. At start-up, the regulator always operates in a 2-phase CCM mode, regardless of control signal assertion levels. During this internal, the SOFT cap is charged by 41A current source. If the SOFT capacitor is selected to be 20nF, the SOFT ramp will be at 2mV/s for a soft-start time of 600s. Once VOUT is within 10% of the boot voltage for 13 PWM cycles (43s for frequency = 300kHz), then CLK_EN# is pulled LOW and the SOFT cap is charged/discharged by approximately 200A. Therefore, VOUT slews at +10mV/s to the voltage set by the VID pins. Approximately 7ms later, PGOOD is asserted HIGH. Typical start-up timing is shown in Figure 34.
0 0 1 1
A fully-differential amplifier implements core voltage sensing for precise voltage control at the microprocessor die. The inputs to the amplifier are the VSEN and RTN pins. As the load current increases from zero, the output voltage will droop from the VID table value by an amount proportional to current to achieve the IMVP-6+ load line. The ISL6262A provides for current to be measured using either resistors in series with the channel inductors as shown in the application circuit of Figure 33, or using the intrinsic series resistance of the inductors as shown in the application circuit of Figure 32. In both cases, signals representing the inductor currents are summed at VSUM, which is the non-inverting input to the DROOP amplifier shown in the "Functional Block Diagram" on page 8 of Figure 1. The voltage at the DROOP pin minus the output voltage, VO, is a high-bandwidth
FN6343.1 December 23, 2008
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ISL6262A
analog of the total inductor current. This voltage is used as an input to a differential amplifier to achieve the IMVP-6+ load line, and also as the input to the overcurrent protection circuit. When using inductor DCR current sensing, a single NTC element is used to compensate the positive temperature coefficient of the copper winding thus maintaining the load-line accuracy. In addition to monitoring the total current (used for DROOP and overcurrent protection), the individual channel average currents are also monitored and used for balancing the load between channels. The IBAL circuit will adjust the channel pulse-widths up or down relative to the other channel to cause the voltages presented at the ISEN pins to be equal. The ISL6262A controller can be configured for two-channel operation, with the channels operating 180 apart. The channel PWM frequency is determined by the value of RFSET connected to pin VW as shown in Figure 32 and Figure 33. Input and output ripple frequencies will be the channel PWM frequency multiplied by the number of active channels. capacitor through the inductors, and the switching frequency will be proportionately reduced, thus greatly reducing both conduction and switching losses. If ISEN2 is pulled to 5V, the ISL6262A operates at 1-phase-only mode. The ISL6262A always enables the diode emulation mode of phase 1 in always-1-phase configuration. Smooth mode transitions are facilitated by the R3 TechnologyTM, which correctly maintains the internally synthesized ripple currents throughout mode transitions. The controller is thus able to deliver the appropriate current to the load throughout mode transitions. The controller contains embedded mode-transition algorithms that maintain voltage-regulation for all control signal input sequences and durations. Mode-transition sequences often occur in concert with VID changes; therefore the timing of the mode transitions of ISL6262A has been carefully designed to work in concert with VID changes. For example, transitions into single-phase will be delayed until the VID induced voltage ramp is complete. This allows the associated output capacitor charging current to be shared by both inductor paths. While in single-phase automatic-DCM mode, VID changes will initiate an immediate return to two-phase CCM mode. This ensures that both inductor paths share the output capacitor charging current and are fully active for the subsequent load current increases. The controller contains internal counters that prevent spurious control signal glitches from resulting in unwanted mode transitions. Control signals of less than two switching periods do not result in phase-idling. Signals of less than seven switching periods do not result in implementation of automatic-DCM mode. While transitioning to single-phase operation, the controller smoothly transitions current from the idling-phase to the active-phase, and detects the idling-phase zero-current condition. During transitions into automatic-DCM or forced-CCM mode, the timing is carefully adjusted to eliminate output voltage excursions. When a phase is added, the current balance between phases is quickly restored.
High Efficiency Operation Mode
The ISL6262A has several operating modes to optimize efficiency. The controller's operational modes are designed to work in conjunction with the Intel(R) IMVP-6+ control signals to maintain the optimal system configuration for all IMVP-6+ conditions. These operating modes are established by the IMVP-6+ control signal inputs such as PSI#, DPRSLPVR, and DPRSTP# as shown in Table 2. At high current levels, the system will operate with both phases fully active, responding rapidly to transients and deliver the maximum power to the load. At reduced load-current levels, one of the phases may be idled. This configuration will minimize switching losses, while still maintaining transient response capability. At the lowest current levels, the controller automatically configures the system to operate in single-phase automatic-DCM mode, thus achieving the highest possible efficiency. In this mode of operation, the lower MOSFET will be configured to automatically detect and prevent discharge current flowing from the output
TABLE 2. CONTROL SIGNAL TRUTH TABLES FOR OPERATION MODES OF ISL6262A IN TWO-PHASE DESIGN DPRSLPVR Intel IMVP-6+ COMPLIANT LOGIC 0 0 1 1 OTHER LOGIC COMMANDS 0 0 1 1 DPRSTP# 1 1 0 0 0 0 1 1 PSI# 1 0 1 0 1 0 1 0 PHASE OPERATION MODES 2-phase CCM 1-phase CCM 1-phase diode emulation 1-phase diode emulation 2-phase CCM 1-phase CCM 2-phase CCM 1-phase CCM EXPECTED CPU MODE Active mode Active mode Deeper sleep mode Deeper sleep mode
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ISL6262A
While PSI# is high, both phases are switching. If PSI# is asserted low and either DPRSTP# or DPRSLPVR are not asserted, the controller will transition to CCM operation with only phase 1 switching, and both MOSFETs of phase 2 will be off. The controller will thus eliminate switching losses associated with the unneeded channel.
VOUT AND VSOFT 10mV/s
For DPRSLPVR LOW, the large signal dV/dt will be 10mV/s. As the output voltage approaches the VID command value, the dV/dt moderates to prevent overshoot. Keeping DPRSLPVR HIGH for voltage transitions into and out of Deeper Sleep will result in low dV/dt output voltage changes with resulting minimized audio noise. For fastest recovery from Deeper Sleep to Active mode, holding DPRSLPVR LOW results in maximum dV/dt. Therefore, the ISL6262A is IMVP-6+ compliant for DPRSTP# and DPRSLPVR logic. Intersil's R3 TechnologyTM has intrinsic voltage feedforward. As a result, high-speed input voltage steps do not result in significant output voltage perturbations. In response to load current step increases, the ISL6262A will transiently raise the switching frequency so that response time is decreased and current is shared by two channels.
-2.5mV/s
2.5mV/s DPRSLPVR
VID #
Protection
FIGURE 35. DEEPER SLEEP TRANSITION SHOWING DPRSLPVR'S EFFECT ON EXIT SLEW RATE
The ISL6262A provides overcurrent, overvoltage, undervoltage protection and over-temperature protection as shown in Table 3. Overcurrent protection is tied to the voltage droop which is determined by the resistors selected as described in "Component Selection and Application" on page 19". After the load-line is set, the OCSET resistor can be selected to detect overcurrent at any level of droop voltage. An overcurrent fault will occur when the load current exceeds the overcurrent setpoint voltage while the regulator is in a 2-phase mode. While the regulator is in a 1-phase mode of operation, the overcurrent setpoint is automatically reduced to 66% of two-phase overcurrent level. For overcurrents less than 2.5 times the OCSET level, the over-load condition must exist for 120s in order to trip the OC fault latch. This is shown in Figure 24.
When PSI#, DPRSTP#, and DPRSLPVR are all asserted, the controller will transition to single-phase DCM mode. In this mode, both MOSFETs associated with phase 2 are off, and the ISL6262A turns off the lower MOSFET of Channel 1 whenever the Channel 1 current decays to zero. As load is further reduced, the phase 1 channel switching frequency decreases to maintain high efficiency.
Dynamic Operation
See Figure 35. The ISL6262A responds to changes in VID command voltage by slewing to new voltages with a dV/dt set by the SOFT capacitor and by the state of DPRSLPVR. With CSOFT = 15nF and DPRSLPVR HIGH, the output voltage will move at 2.8mV/s for large changes in voltage.
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6262A FAULT DURATION PRIOR TO PROTECTION Overcurrent fault Way-Overcurrent fault Overvoltage fault (1.7V) 120s <2s Immediately PROTECTION ACTIONS PWM1, PWM2 three-state, PGOOD latched low PWM1, PWM2 three-state, PGOOD latched low Low-side MOSFET on until Vcore <0.85V, then PWM three-state, PGOOD latched low (OV to 1.7V always) PWM1, PWM2 three-state, PGOOD latched low PWM1, PWM2 three-state, PGOOD latched low PWM1, PWM2 three-state, PGOOD latched low VR_TT# goes low FAULT RESET VR_ON toggle or VDD toggle VR_ON toggle or VDD toggle VDD toggle
Overvoltage fault (+200mV) Undervoltage fault (-300mV) Unbalance fault (7.5mV) Over-temperature fault (NTC <1.18V)
1ms 1ms 1ms Immediately
VR_ON toggle or VDD toggle VR_ON toggle or VDD toggle VR_ON toggle or VDD toggle N/A
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ISL6262A
For overloads exceeding 2.5xthe set level, the PWM outputs will immediately shut off and PGOOD goes low to maximize protection due to hard shorts. In addition, excessive phase unbalance (for example, due to gate driver failure) will be detected in two-phase operation and the controller will be shutdown after one millisecond's detection of the excessive phase current unbalance. The phase unbalance is detected by the voltage on the ISEN pins if the difference is greater than 9mV. Undervoltage protection is independent of the overcurrent limit. If the output voltage is less than the VID set value by 300mV or more, a fault will latch after one millisecond in that condition. The PWM outputs will turn off and PGOOD will go low. Note that most practical core regulators will have the overcurrent set to trip before the -300mV undervoltage limit. There are two levels of overvoltage protection and response. 1. For output voltage exceeding the set value by +200mV for one millisecond, a fault is declared. All of the above faults have the same action taken: PGOOD is latched low and the upper and lower power MOSFETs are turned off so that inductor current will decay through the MOSFET body diodes. This condition can be reset by bringing VR_ON low or by bringing VDD below 4V. When these inputs are returned to their high operating levels, a soft-start will occur. 2. The second level of overvoltage protection behaves differently (see Figure 25). If the output exceeds 1.7V, an OV fault is immediately declared, PGOOD is latched low and the low-side MOSFETs are turned on. The low-side MOSFETs will remain on until the output voltage is pulled down below about 0.85V, at which time all MOSFETs are turned off. If the output again rises above 1.7V, the protection process is repeated. This offers the maximum amount of protection against a shorted high-side MOSFET while preventing output ringing below ground. The 1.7V OV is not reset with VR_ON, but requires that VDD be lowered to reset. The 1.7V OV detector is active at all times that the controller is enabled including after one of the other faults occurs so that the processor is protected against high-side MOSFET leakage while the MOSFETs are commanded off. The ISL6262A has a thermal throttling feature. If the voltage on the NTC pin goes below the 1.2V over-temperature threshold, the VR_TT# pin is pulled low indicating the need for thermal throttling to the system oversight processor. No other action is taken within the ISL6262A in response to NTC pin voltage. given by: Vpmon = VCCSENSE * (Vdroop - VO) * 17.5. In always-single-phase design, the output voltage PMON pin is given by: Vpmon = VCCSENSE * (Vdroop-VO) * 35. The power consumed by the CPU can be calculated by: Pcpu = Vpmon / (17.5 * 0.0021) (Watt), where 0.0021 is the typical load line slope. The power monitor load regulation is approximately 7. Within its sourcing/sinking current capability range, when the power monitor loading changes to 1mA, the output of the power monitor will change to 7mV. The 7 impedance is associated with the layout and package resistance of PMON inside the IC. In practical applications, compared to the load resistance on the PMON pin, 7 output impedance contributes no significant error.
Component Selection and Application
Soft-Start and Mode Change Slew Rates
The ISL6262A uses two slew rates for various modes of operation. The first is a slow slew rate used to reduce in-rush current during start-up. It is also used to reduce audible noise when entering or exiting Deeper Sleep Mode. A faster slew rate is used to exit out of Deeper Sleep and to enhance system performance by achieving active mode regulation more quickly. Note that the SOFT cap current is bidirectional. The current is flowing into the SOFT capacitor when the output voltage is commanded to rise and out of the SOFT capacitor when the output voltage is commanded to fall. The two slew rates are determined by commanding one of two current sources onto the SOFT pin. As can be seen in Figure 36, the SOFT pin has a capacitance to ground. Also, the SOFT pin is the input to the error amplifier and is, therefore, the commanded system voltage. Depending on the state of the system (that is, Start-Up or Active mode) and the state of the DPRSLPVR pin, one of the two currents shown in Figure 36 will be used to charge or discharge this capacitor, thereby controlling the slew rate of the commanded voltage. These currents can be found under "SOFT-START CURRENT" on page 4 of the Electrical Specifications table.
ISL6262A
ISS
I2
ERROR AMPLIFIER +
Power Monitor
The power monitor signal is an analog output. Its magnitude is proportional to the product of VCCSENSE and the voltage difference between Vdroop and VO, which is the programmed voltage droop value, equal to load current multiplied by the load line impedance (for example 2.1m). The output voltage of the PMON pin in two-phase design is
CSOFT
SOFT
+ VREF
FIGURE 36. SOFT PIN CURRENT SOURCES FOR FAST AND SLOW SLEW RATES
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ISL6262A
The first current, labeled ISS, is given in the Table Electrical Specifications on page 3 as 42A. This current is used during soft-start. The second current, I2 sums with ISS to get the larger of the two currents, labeled IGV in the Table Electrical Specifications on page 3 . This total current is typically 205A with a minimum of 180A. The IMVP-6+ specification reveals the critical timing associated with regulating the output voltage. The symbol, SLEWRATE, as given in the IMVP-6+ specification will determine the choice of the SOFT capacitor, CSOFT, by Equation 1.
I GV C SOFT = ----------------------------------SLEWRATE (EQ. 1)
noise immunity, the 3.3V supply should be decoupled to digital ground rather than to analog ground. As mentioned in "Theory of Operation" on page 16, CLK_EN# is logic level high at start-up until approximately 43s after the VCC-core is in regulation at the Boot level. Approximately 43s after VCC-core are within regulation, CLK_EN# goes low, triggering an internal timer for the IMVP6_PWRGD signal. This timer allows IMVP-6_PWRGD to go high approximately 6.8ms after CLK_EN# goes low.
Static Mode of Operation - Processor Die Sensing
Die sensing is the ability of the controller to regulate the core output voltage at a remotely sensed point. This allows the voltage regulator to compensate for various resistive drops in the power path and ensure that the voltage seen at the CPU die is the correct level independent of load current. The VSEN and RTN pins of the ISL6262A are connected to Kelvin sense leads at the die of the processor through the processor socket. These signal names are Vcc_sense and Vss_sense respectively. This allows the voltage regulator to tightly control the processor voltage at the die, independent of layout inconsistencies and voltage drops. This Kelvin sense technique provides for extremely tight load line regulation. These traces should be laid out as noise sensitive traces. For optimum load line regulation performance, the traces connecting these two pins to the Kelvin sense leads of the processor must be laid out away from rapidly rising voltage nodes, (switching nodes) and other noisy traces. To achieve optimum performance, place common mode and differential mode filters to analog ground on VSEN and RTN as shown in Figure 37. Intersil recommends the use of the Ropn1 and Ropn2 connected to VOUT and ground as shown in Figure 37. These resistors provide voltage feedback in the event that the system is powered up without a processor installed. These resistors typically range from 20 to 100.
Using a SLEWRATE of 10mV/s and the typical IGV value given in the Electrical Specification table of 205A, CSOFT is as shown in Equation 2.
C SOFT = 205A ( 10mV 1s ) (EQ. 2)
A choice of 0.015F would guarantee a SLEWRATE of 10mV/s is met for the minimum IGV value given in the Electrical Specification table. This choice of CSOFT will then control the Start-Up slewrate as well. One should expect the output voltage to slew to the Boot value of 1.2V at a rate given by Equation 3.
I SS 41A dV ------- = ------------------- = ---------------------- = 2.8mV s 0.015F C SOFT dt (EQ. 3)
Selecting RBIAS
To properly bias the ISL6262A, a reference current is established by placing a 147k, 1% tolerance resistor from the RBIAS pin to ground. This will provide a highly accurate 10A current source from which the OCSET reference current can be derived. Care should be taken in layout that the resistor is placed very close to the RBIAS pin and that a good quality signal ground is connected to the opposite side of the RBIAS resistor. Do not connect any other components to this pin as this would negatively impact performance. Capacitance on this pin would create instabilities and should be avoided.
Start-Up Operation - CLK_EN# and PGOOD
The ISL6262A provides a 3.3V logic output pin for CLK_EN#. The 3V3 pin allows for a system 3.3V source to be connected to separated circuitry inside the ISL6262A, solely devoted to the CLK_EN# function. The output is a 3.3V CMOS signal with 4mA sourcing and sinking capability. This implementation removes the need for an external pull-up resistor on this pin, and due to the normal level of this signal being a low, removes the leakage path from the 3.3V supply to ground through the pull-up resistor. This reduces the 3.3V supply current that would occur under normal operation with a pull-up resistor and prolongs battery life. For
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ISL6262A
ISEN1 ISEN1 ISEN2 10A OC + VSUM INTERNAL TO ISL6262A + + + 1+ 1RTN VDIFF 330pF 0.01F Ropn1 330pF VCC_SENSE ROPN2 VSS_SENSE TO PROCESSOR SOCKET KELVIN CONNECTIONS TO VOUT ESR VSEN VO' Rdrp1 VO' + DROOP VSUM RSERIES VSUM OCSET ROCSET VO' ISEN2
IPHASE1
L1
+
Vdcr1 DCR
RS RL1 ISEN1 L2 RL2 ISEN2 C L1
-
DFB
RO1
DROOP Rdrp2 Cn RNTC IPHASE2 RPAR RS VSUM
VO' DCR + Vdcr2 VOUT RO2 CBULK VO'
CL2
FIGURE 37. SIMPLIFIED SCHEMATIC FOR DROOP AND DIE SENSING WITH INDUCTOR DCR CURRENT SENSING
Setting the Switching Frequency - FSET
The R3 modulator scheme is not a fixed frequency PWM architecture. The switching frequency can increase during the application of a load to improve transient performance. It also varies slightly due to changes in input and output voltage and output current, but this variation is normally less than 10% in continuous conduction mode. The resistor connected between the VW and COMP pins of the ISL6262A adjusts the switching window, and therefore adjusts the switching frequency (Figure 32). The RFSET resistor that sets up the switching frequency of the converter operating in CCM can be determined using Equation 4, where RFSET is in k and the switching period is in s.
R FSET ( k ) = ( period ( s ) - 0.29 ) * 2.33 (EQ. 4)
Proper selection and placement of the NTC thermistor allows for detection of a designated temperature rise by the system. Figure 38 shows the thermal throttling feature with hysteresis. At low temperature, SW1 is on and SW2 connects to the 1.2V side. The total current going into NTC pin is 60A. The voltage on the NTC pin is higher than the threshold voltage of 1.2V and the comparator output is low. VR_TT# is pulling up high by the external resistor.
54A
6A
SW1 NTC + VNTC RNTC Rs 1.24V SW2 1.20V INTERNAL TO ISL6262A +
VR_TT#
For 300kHz operation, Rfset is suggested to be 6.81k. In discontinuous conduction mode (DCM), the ISL6262A runs in period stretching mode. The switching frequency is dependent on the load current level. In general, the lighter load, the slower switching frequency. Therefore, the switching loss is much reduced for the light load operation, which is important for conserving the battery power in the portable application.
Voltage Regulator Thermal Throttling
lntel(R) IMVP-6+ technology supports thermal throttling of the processor to prevent catastrophic thermal damage to the voltage regulator. The ISL6262A features a thermal monitor that senses the voltage change across an externally placed negative temperature coefficient (NTC) thermistor.
FIGURE 38. CIRCUITRY ASSOCIATED WITH THE THERMAL THROTTLING FEATURE IN ISL6262A
When the temperature increases, the NTC resistor value on the NTC pin decreases. Thus, the voltage on the NTC pin decreases to a level lower than 1.2V. The comparator output changes polarity and turns SW1 off and connects SW2 to 1.24V. This pulls VR_TT# low and sends the signal to start thermal throttle. There is a 6A current reduction on the NTC
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pin and 20mV voltage increase on the threshold voltage of the comparator in this state. The VR_TT# signal will be used to change the CPU operation and decrease the power consumption. When the temperature goes down, the NTC thermistor voltage will eventually go up. When the NTC pin voltage increases to 1.24V, the comparator output will then be able to flip back. Such a temperature hysteresis feature of VR_TT# is illustrated in Figure 39. T1 represents the higher temperature point at which the VR_TT# goes from low to high due to the system temperature rise. T2 represents the lower temperature point at which the VR_TT# goes high from low because the system temperature decreases to the normal level.
VR_TT# LOGIC_1
For those cases where the constant b is not accurate enough to approximate the resistor value, the manufacturer provides the resistor ratio information at different temperatures. The nominal NTC resistor value may be expressed in another way shown in Equation 10.
2.96k R NTCTo = ---------------------------------------------------------------------- - R NTC ( T 2 ) R NTC ( T 1 ) (EQ. 10)
where R NTC ( T ) is the normalized NTC resistance to its nominal value. Most data sheets of the NTC thermistor give the normalized resistor value based on its value at +25C. Once the NTC thermistor resistor is determined, the series resistor can be derived by: Equation 11.
1.2V R S = -------------- - R NTC ( T1 ) = 20k - R NTC_T 60A 1 (EQ. 11)
LOGIC_0 T2 T1 T (C)
Once RNTCTo and Rs is designed, the actual NTC resistance at T2 and the actual T2 temperature can be found in: Equations 12, and 13.
R NTC_T
2
= 2.96k + R NTC_T
1
(EQ. 12)
FIGURE 39. TEMPERATURE HYSTERESIS OF VR_TT#
Usually, the NTC thermistor's resistance can be approximated by Equation 5.
R NTC ( T ) = R NTCTo * e 1 1 b * ------------------- - ----------------------- T + 273 To + 273 (EQ. 5)
1 T 2_actual = ---------------------------------------------------------------------------------- - 273 R NTC_T 2 1 -- ln ------------------------- + 1 ( 273 + To ) b R NTCTo
(EQ. 13)
T is the temperature of the NTC thermistor and b is a parameter constant depending on the thermistor material. To is the reference temperature in which the approximation is derived. The most common temperature for To is +25C. For example, there are commercial NTC thermistor products with b = 2750k, b = 2600k, b = 4500k or b = 4250k. From the operation principle of the VR_TT# circuit explained, the NTC resistor satisfies Equation 6 and 8.
1.2V R NTC ( T 1 ) + R S = -------------- = 20k 60A 1.24V R NTC ( T 2 ) + R S = --------------- = 22.96k 54A (EQ. 6)
For example, if using Equations 9, 10 and 11 to design a thermal throttling circuit with the temperature hysteresis +100C to +105C, since T1 = +105C and T2 = +100C, and if we use a Panasonic NTC with b = 4700, Equation 9 gives the required NTC nominal resistance as RNTC_To = 459k. In fact, the data sheet gives the resistor ratio value at +100C to +105C, which is 0.03956 and 0.03322 respectively. The b value 4700k in the Panasonic data sheet only covers to +85C. Therefore, using Equation 10 is more accurate for +100C design, the required NTC nominal resistance at +25C is 467k. The closest NTC resistor value from the manufacturer is 467k. So the series resistance is given by Equation 14.
R S = 20k - R NTC_105C = 20k - 15.65k = 4.35k (EQ. 14)
(EQ. 7)
From Equation 6 and Equation 7, Equation 8 can be derived,
R NTC ( T 2 ) - R NTC ( T 1 ) = 2.96k (EQ. 8)
Using Equation 5 into Equation 8, the required nominal NTC resistor value can be obtained by: Equation 9.
2.96k * e R NTCTo = ----------------------------------------------------------------------------e
1b * ---------------------- T + 273 2 1b * ---------------------- T + 273 o
The closest standard resistor is 4.42k. Furthermore, the NTC resistance at T2 is given by Equation 15.
R NTC_T2 = 2.96k + R NTC_T1 = 18.16k (EQ. 15)
-e
1b * ---------------------- T + 273 1
(EQ. 9)
Therefore, the NTC branch is designed to have a 470k NTC and 4.42k resistor in series. The part number of the NTC thermistor is ERTJ0EV474J. It is a 0402 package. The NTC
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FN6343.1 December 23, 2008
ISL6262A
10A OC +
OCSET RS VSUM + DROOP VSUM RS = -------2
EQV
INTERNAL TO ISL6262A + 1+ 1-
DFB DROOP + Rdrp2 Cn VN Vdcr EQV =I OUT DCR x ------------2
+ +
VDIFF
RTN VSEN
VO'
Rdrp1
-
( Rntc + Rseries ) x Rpar Rn = ----------------------------------------------------------------------( Rntc + Rseries ) + Rpar
VO' RO RO EQV = -------2
FIGURE 40. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DCR SENSING
thermistor should be placed in the spot which gives the best indication of the temperature of voltage regulator circuit.
Static Mode of Operation - Static Droop Using DCR Sensing
As previously mentioned, the ISL6262A has an internal differential amplifier which provides for very accurate voltage regulation at the die of the processor. The load line regulation is also accurate for both two-phase and single-phase operation. The process of selecting the components for the appropriate load line droop is explained here. For DCR sensing, the process of compensation for DCR resistance variation to achieve the desired load line droop has several steps and is somewhat iterative. The two-phase solution using DCR sensing is shown in Figure 37. There are two resistors connecting to the terminals of inductor of each phase. These are labeled RS and RO. These resistors are used to obtain the DC voltage drop across each inductor. Each inductor will have a certain level of DC current flowing through it, and this current, when multiplied by the DCR of the inductor, creates a small DC voltage drop across the inductor terminal. When this voltage is summed with the other channels DC voltages, the total DC load current can be derived. RO is typically 1 to 10. This resistor is used to tie the outputs of all channels together and thus create a summed average of the local CORE voltage output. RS is determined through an understanding of both the DC and transient load currents. This value will be covered in the next section. However, it is important to keep in mind that the output of each of these RS resistors are tied together to create the VSUM voltage node. With both the outputs of RO and RS tied together, the simplified model for the droop circuit can be derived. This is presented in Figure 40.
Figure 40 shows the simplified model of the droop circuitry. Essentially one resistor can replace the RO resistors of each phase and one RS resistor can replace the RS resistors of each phase. The total DCR drop due to load current can be replaced by a DC source, the value of which is given by: Equation 16.
I OUT * DCR V DCR_EQU = -------------------------------2 (EQ. 16)
For the convenience of analysis, the NTC network comprised of Rntc, Rseries and Rpar, given in Figure 37, is labeled as a single resistor Rn in Figure 40. The first step in droop load line compensation is to adjust Rn, ROEQV and RSEQV such that sufficient droop voltage exists even at light loads between the VSUM and VO' nodes. As a rule of thumb, we start with the voltage drop across the Rn network, VN, to be 0.5 to 0.8 times VDCR_EQU. This ratio provides for a fairly reasonable amount of light load signal from which to arrive at droop. The resultant NTC network resistor value is dependent on the temperature and given by Equation 17.
( R series + R ntc ) * R par R n ( T ) = -------------------------------------------------------------R series + R ntc + R par (EQ. 17)
For simplicity, the gain of Vn to the Vdcr_equ is defined by G1, also dependent on the temperature of the NTC thermistor.
Rn ( T ) G 1 ( T ) = -----------------------------------------R n ( T ) + RS EQV DCR ( T ) = DCR 25C * ( 1 + 0.00393*(T-25) ) (EQ. 18)
(EQ. 19)
Therefore, the output of the droop amplifier divided by the total load current can be expressed as shown in Equation 20, where Rdroop is the realized load line slope and 0.00393 is the temperature coefficient of the copper.
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FN6343.1 December 23, 2008
ISL6262A
DCR 25 R droop = G 1 ( T ) * ------------------- * ( 1 + 0.00393*(T-25) ) * k droopamp 2 (EQ. 20)
PCB traces sensing the inductor voltage should be going directly to the inductor pads. Once the board has been laid out, some adjustments may be required to adjust the full load droop voltage. This is fairly easy and can be accomplished by allowing the system to achieve thermal equilibrium at full load, and then adjusting Rdrp2 to obtain the appropriate load line slope. To see whether the NTC has compensated the temperature change of the DCR, the user can apply full load current and wait for the thermal steady state and see how much the output voltage will deviate from the initial voltage reading. A good compensation can limit the drift to 2mV. If the output voltage is decreasing with temperature increase, that ratio between the NTC thermistor value and the rest of the resistor divider network has to be increased. The user should follow the evaluation board value and layout of NTC as much as possible to minimize engineering time. The 2.1mV/A load line should be adjusted by Rdrp2 based on maximum current, (not based on small current steps like 10A), as the droop gain might vary between each 10A step. Basically, if the max current is 40A, the required droop voltage is 84mV. The user should have 40A load current on and look for 84mV droop. If the drop voltage is less than 84mV, for example 80mV, the new value will be calculated by: using Equation 26.
84mV Rdrp2_new = --------------- ( Rdrp1 + Rdrp2 ) - Rdrp1 80mV (EQ. 26)
To achieve the droop value independent from the temperature of the inductor, it is equivalently expressed by Equation 21.
G 1 ( T ) * ( 1 + 0.00393*(T-25) ) G 1t arg et (EQ. 21)
The non-inverting droop amplifier circuit has the gain Kdroopamp expressed as:
R drp2 k droopamp = 1 + --------------R drp1
G1target is the desired gain of Vn over IOUT * DCR/2. Therefore, the temperature characteristics of gain of Vn is described by Equation 22.
G 1t arg et G 1 ( T ) = -----------------------------------------------------( 1 + 0.00393*(T-25) ) (EQ. 22)
For the G1target = 0.76: Rntc = 10k with b = 4300, Rseries = 2.61k, and Rpar = 11k RSEQV = 1825 generates a desired G1, close to the feature specified in Equation 22. The actual G1 at +25C is 0.769. For different G1 and NTC thermistor preferences, the design file to generate the proper value of Rntc, Rseries, Rpar, and RSEQV is provided by Intersil. Then, the individual resistors from each phase to the VSUM node, labeled RS1 and RS2 in Figure 37, are then given by Equation 23.
R S = 2 * RS EQV (EQ. 23)
So, Rs = 3650. Once we know the attenuation of the RS and RN network, we can then determine the droop amplifier gain required to achieve the load line. Setting Rdrp1 = 1k_1%, then Rdrp2 can be found using Equation 24.
2 * R droop Rdrp2 = ----------------------------------------------- - 1 * R drp1 DCR * G1 ( 25C ) (EQ. 24)
Droop Impedance (Rdroop) = 0.0021 (V/A) as per the Intel IMVP-6+ specification, DCR = 0.0008 typical for a 0.36H inductor, Rdrp1 = 1k and the attenuation gain (G1) = 0.77, Rdrp2 is then given by Equation 25.
2 * R droop Rdrp2 = -------------------------------------- - 1 * 1k 5.82k 0.0008 * 0.769 (EQ. 25)
For the best accuracy, the effective resistance on the DFB and VSUM pins should be identical so that the bias current of the droop amplifier does not cause an offset voltage. In the previous example, the resistance on the DFB pin is Rdrp1 in parallel with Rdrp2, that is, 1k in parallel with 5.82k or 853. The resistance on the VSUM pin is Rn in parallel with RSEQV or 5.87k in parallel with 1.825k or 1392. The mismatch in the effective resistances is 1404 - 53 = 551. Do not let the mismatch get larger than 600. To reduce the mismatch, multiply both Rdrp1 and Rdrp2 by the appropriate factor. The appropriate factor in the example is 1404/853 = 1.65. In summary, the predicted load line with the designed droop network parameters based on the Intersil design tool is shown in Figure 41
Note, we choose to ignore the RO resistors because they do not add significant error. These designed values in Rn network are very sensitive to the layout and coupling factor of the NTC to the inductor. As only one NTC is required in this application, this NTC should be placed as close to the Channel 1 inductor as possible and
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FN6343.1 December 23, 2008
ISL6262A
.
2.25
LOAD LINE (mV/A)
2.2
2.15
2.1
2.05 0 20 40 60 80 100 INDUCTOR TEMPERATURE (C)
prevent the output voltage from going lower than the specification. This cap needs to be a high grade capacitor like X7R with low tolerance. There is another consideration in order to achieve better time constant match mentioned previously. The NPO/COG (class-I) capacitors have only 5% tolerance and a very good thermal characteristics. But those capacitors are only available in small capacitance values. In order to use such capacitors, the resistors and thermistors surrounding the droop voltage sensing and droop amplifier has to be resized up to 10X to reduce the capacitance by 10X. But attention has to be paid in balancing the impedance of droop amplifier in this case.
FIGURE 41. LOAD LINE PERFORMANCE WITH NTC THERMAL COMPENSATION
Dynamic Mode of Operation - Compensation Parameters
Considering the voltage regulator as a black box with a voltage source controlled by VID and a series impedance, in order to achieve the 2.1mV/A load line, the impedance needs to be 2.1m. The compensation design has to target the output impedance of the converter to be 2.1m. There is a mathematical calculation file available to the user. The power stage parameters such as L and Cs are needed as the input to calculate the compensation component values. Attention has to be paid to the input resistor to the FB pin. Too high of a resistor will cause an error to the output voltage regulation because of bias current flowing in the FB pin. It is better to keep this resistor below 3k when using this file.
Dynamic Mode of Operation - Dynamic Droop Using DCR Sensing
Droop is very important for load transient performance. If the system is not compensated correctly, the output voltage could sag excessively upon load application and potentially create a system failure. The output voltage could also take a long period of time to settle to its final value. This could be problematic if a load dump were to occur during this time. This situation would cause the output voltage to rise above the no load setpoint of the converter and could potentially damage the CPU. The L/DCR time constant of the inductor must be matched to the Rn*Cn time constant as shown in Equation 27.
R n * RS EQV L ------------- = --------------------------------- * C n DCR R n + RS EQV (EQ. 27)
Static Mode of Operation - Current Balance Using DCR or Discrete Resistor Current Sensing
Current Balance is achieved in the ISL6262A through the matching of the voltages present on the ISEN pins. The ISL6262A adjusts the duty cycles of each phase to maintain equal potentials on the ISEN pins. RL and CL around each inductor, or around each discrete current resistor, are used to create a rather large time constant such that the ISEN voltages have minimal ripple voltage and represent the DC current flowing through each channel's inductor. For optimum performance, RL is chosen to be 10k and CL is selected to be 0.22F. When discrete resistor sensing is used, a capacitor most likely needs to be placed in parallel with RL to properly compensate the current balance circuit. ISL6262A uses RC filter to sense the average voltage on phase node and forces the average voltage on the phase node to be equal for current balance. Even though the ISL6262A forces the ISEN voltages to be almost equal, the inductor currents will not be exactly equal. Using DCR current sensing as an example, two errors have to be added to find the total current imbalance. 1. Mismatch of DCR: If the DCR has a 5% tolerance then the resistors could mismatch by 10% worst case. If each phase is carrying 20A then the phase currents mismatch by 20A*10% = 2A. 2. Mismatch of phase voltages/offset voltage of ISEN pins: The phase voltages are within 2mV of each other by
Solving for Cn we now have Equation 28.
L ------------DCR C n = ---------------------------------R n * RS EQV ---------------------------------R n + RS EQV (EQ. 28)
Note, RO was neglected. As long as the inductor time constant matches the Cn, Rn and Rs time constants as given previously, the transient performance will be optimum. As in the static droop case, this process may require a slight adjustment to correct for layout inconsistencies. For the example of L = 0.36H with 0.8m DCR, Cn is calculated in Equation 29.
0.36H ------------------0.0008 C n = --------------------------------------------------------------------- 330nF parallel ( 5.823K, 1.825K ) (EQ. 29)
The value of this capacitor is selected to be 330nF. As the inductors tend to have 20% to 30% tolerances, this cap generally will be tuned on the board by examining the transient voltage. If the output voltage transient has an initial dip, lower than the voltage required by the load line, and slowly increases back to the steady state, the capacitor is too small and vice versa. It is better to have the capacitor value a little bigger to cover the tolerance of the inductor to 25
FN6343.1 December 23, 2008
ISL6262A
current balance circuit. The error current that results is given by 2mV/DCR. If DCR = 1m then the error is 2A. In the previous example, the two errors add to 4A. For the two phase DC/DC, the currents would be 22A in one phase and 18A in the other phase. In the above analysis, the current balance can be calculated with 2A/20A = 10%. This is the worst case calculation. For example, the actual tolerance of two 10% DCRs is 10%*sqrt(2) = 7%. There are provisions to correct the current imbalance due to layout or to purposely divert current to certain phase for better thermal management. Customer can put a resistor in parallel with the current sensing capacitor on the phase of interest in order to purposely increase the current in that phase. If the PC board trace resistance from the inductor to the microprocessor are significantly different between two phases, the current will not be balanced perfectly. Intersil has a proprietary method to achieve the perfect current sharing in case of severe unbalanced layout. When choosing the current sense resistor, both the tolerance of the resistance and the TCR are important. Also, the current sense resistor's combined tolerance at a wide temperature range should be calculated. Solving for the Rdrp2 value, Rdroop = 0.0021(V/A) as per the Intel IMVP-6+ specification, Rsense = 0.001 and Rdrp1 =1k, we obtain in Equation 32.
R drp2 = ( K droopamp - 1 ) * R drp1 = 3.2k (EQ. 32)
These values are extremely sensitive to layout. Once the board has been laid out, some tweaking may be required to adjust the full load droop. This is fairly easy and can be accomplished by allowing the system to achieve thermal equilibrium at full load, and then adjusting Rdrp2 to obtain the desired droop value.
Fault Protection - Overcurrent Fault Setting
As previously described, the overcurrent protection of the ISL6262A is related to the droop voltage. Previously we have calculated that the droop voltage = ILoad*Rdroop, where Rdroop is the load line slope specified as 0.0021 (V/A) in the Intel IMVP-6+ specification. Knowing this relationship, the overcurrent protection threshold can be set up as a voltage droop level. Knowing this voltage droop level, one can program in the appropriate drop across the ROC resistor. This voltage drop will be referred to as Voc. Once the droop voltage is greater than Voc, the PWM drives will turn off and PGOOD will go low. The selection of ROC is given in Equation 33. Assuming we desire an overcurrent trip level, IOC, of 55A, and knowing from the Intel Specification that the load line slope, Rdroop is 0.0021 (V/A), we can then calculate for ROC as shown in Equation 33.
I OC * R droop 55 * 0.0021 R OC = ---------------------------------- = ------------------------------ = 11.5k -6 10A 10 * 10 (EQ. 33)
Droop Using Discrete Resistor Sensing - Static/ Dynamic Mode of Operation
Figure 42 shows the equivalent circuit of a discrete current sense approach. Figure 33 shows a more detailed schematic of this approach. Droop is solved the same way as the DCR sensing approach with a few slight modifications. First, because there is no NTC required for thermal compensation, the Rn resistor network in the previous section is not required. Second, because there is no time constant matching required, the Cn component is not matched to the L/DCR time constant. This component does indeed provide noise immunity and therefore is populated with a 39pF capacitor. The RS values in the previous section, RS = 1.5k_1%, are sufficient for this approach. Now the input to the droop amplifier is essentially the Vrsense voltage. This voltage is given by Equation 30.
R sense Vrsense EQV = ------------------- * I OUT 2 (EQ. 30)
Note: If the droop load line slope is not -0.0021 (V/A) in the application, the overcurrent setpoint will differ from predicted.
The gain of the droop amplifier, Kdroopamp, must be adjusted for the ratio of the Rsense to droop impedance, Rdroop. We use the Equation 31.
R droop K droopamp = ------------------- * 2 R sense (EQ. 31)
26
FN6343.1 December 23, 2008
10A OC +
OCSET
+Voc -Roc RS EQV RS = -------2
VSUM INTERNAL TO ISL6262A + + + 1+ 1+ DROOP DFB DROOP
VSUM
+ Rdrp2 VN Cn -
Vrsense
EQV
=I
OUT
Rsense x ---------------------2
Rdrp1
VDIFF
RTN VSEN
VO'
RO VO'
RO -------EQV = 2
FIGURE 42. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DISCRETE RESISTOR SENSING
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 27
FN6343.1 December 23, 2008
ISL6262A
Package Outline Drawing
L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06
4X 5.5 7.00 A B 6 PIN 1 INDEX AREA 37 36 44X 0.50 48 1 6 PIN #1 INDEX AREA
7.00
4. 30 0 . 15
25 (4X) 0.15 24 TOP VIEW 48X 0 . 40 0 . 1 13
12
0.10 M C A B 4 0.23 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X" 0.10 C BASE PLANE C
( 6 . 80 TYP ) ( 4 . 30 )
0 . 90 0 . 1
SIDE VIEW ( 44X 0 . 5 )
SEATING PLANE 0.08 C
C ( 48X 0 . 23 ) ( 48X 0 . 60 ) TYPICAL RECOMMENDED LAND PATTERN
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX. DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
28
FN6343.1 December 23, 2008

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